*IDENTIFICATION ZXIDEGAL; *TYPE GAL20V8; *PINS %INPUTS% A0 = 2, A1 = 3, A2 = 4, A3 = 9, A4 = 8, A5 = 7, A6 = 6, A7 = 5, %All inputs to CPU% IORQ = 10, M1 = 11, RD = 23, WR = 14, CLKD = 16, %Connect to 22 via 2 gate for delay% %pin 13 (OE) connect to GND% %OUTPUTS % RLAT.T = 15, %Read latch clock (for D8-D15), 74HC573% RLAOE.T = 17, WLAT.T = 18, %Write Latch clock (for D8-D15), 74HC573 (574 not ok)% WLAOE.T = 19, %LWrite latch output enable - see line above% BIFE.T = 20, %Bidir. line transc. enable (for D0-D7) ,74HC245% CLK.T = 22, %CONNECT WITH PIN 1% MFF.R = 21; %Master flip-flop for latch, line driver control, no external connect.% *BOOLEAN-EQUATIONS MFF =/IORQ*M1*/A7*A6*A5*A3*A0*/A4*/A2*/A1*/MFF; %ADR $69 flips,other resets% CLK.E = VCC; CLK = /IORQ*M1*/A7*A6*A5*A3*A0; %For MFF control% RLAT.E = VCC; RLAT = CLKD*/RD*MFF*/A4*/A2*/A1; %Latches D8-D15 in first cycle% RLAOE.E = VCC; /RLAOE = CLKD*/RD*/MFF*/A4*/A2*/A1; %Puts latched data to CPU-s bus in second cycle% WLAT.E = VCC; WLAT = CLKD*/WR*MFF*/A4*/A2*/A1; %delayed% %Latches datas in first cycle% WLAOE.E = VCC; /WLAOE = CLKD*/WR*/MFF*/A4*/A2*/A1; %puts latched datas to HD-s D8-D15 in second cycle% %byte order is reversed by RD & WR !!% BIFE.E = VCC; %Also SELP% /BIFE = CLKD*/RD*A4+ CLKD*/RD*A2+ CLKD*/RD*A1+ CLKD*/RD*/A4*/A2*/A1*MFF+ CLKD*/WR*/MFF; %By read data active in first cycle (MFF high), by write data active in second cycle, by other regs. allways% *END
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